Field
The present disclosure relates generally to memory circuits, and more particularly, to a memory with an improved sense amplifier (SA) enabling scheme.
Background
Memory is a vital component for wireless communication devices (e.g., integrated as part of an application processor in a cell phone). Many of the wireless applications depend on the functionality of a dual port memory, e.g., a memory capable of handling both a read and a write operation within a single clock cycle. A dual port memory typically includes two ports operating with an array of memory cells, which may be simultaneously accessed from both ports. For example, a dual port memory may access two different memory locations (addresses) in a single cycle. In order to reduce the size of the memory, a pseudo-dual port or PDP memory may be used in place of the dual port memory. The core of the PDP memory may be a single-core memory. Accordingly, the memory array of the PDP memory may allow for a single memory access at one instance and not two simultaneous memory accesses as with the dual port memory. The PDP memory may emulate the dual port memory in having two ports. In one implementation, the PDP memory may sequentially perform a read operation and then a write operation to satisfy the dual port function.
With the ever increasing demands for more processing capability, one design challenge is to improve the performance of the PDP memory. For example, reducing the cycle time of the PDP memory may open the PDP memory to more applications.